7244 English-speaking jobs in Madrid

Mixed-Signal Verification Engineer will execute CoSim verification tasks, build and run simulations, debug mixed-signal failures, and collaborate with analog and digital designers. Requires a Master's degree in Electronics Engineering or related field, understanding of digital verification fundamentals, proficiency in System Verilog, and strong debugging skills.

High Frequency Electromagnetics Application Engineer needed. 5-7 years of experience in the high-frequency domain using simulation tools for real-world applications. Expertise with Ansys HFSS, SIwave, Q3D Extractor, or comparable software. MS/PhD in Electrical/Electronic Engineering with specialization in electromagnetics.

Senior Solutions Engineer will guide customers in adopting virtual simulation tools for automotive systems. Responsibilities include customizing tools, collaborating with technical teams, and delivering technical presentations. Requires strong C/C++ and Python programming skills, experience with AUTOSAR, and knowledge of automotive standards and protocols.

Senior Product Manager will drive go-to-market activities for Synopsys' Fluids pre-processing and meshing products. Collaborate with development teams to define roadmaps and strategies, and partner with customers and sales to gather feedback and inform product direction. Serve as a technical expert and thought leader, creating marketing materials and engaging with customers and industry events. Requires a Bachelor's degree in Engineering or related field with experience in CAE simulations, pre-sales support, sales, or customer engagement. Proven experience with commercial CAE tools, especially Ansys Fluent, Fluent Meshing, or similar products, is essential.

Senior Staff Engineer will serve as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs) and working to enable IP as a product development platform. Requires hands-on experience in post-silicon test setups, sound knowledge of Digital/AMS chip design and post-silicon debug, and a BS or MS degree in Electrical Engineering with 6+ years of experience.

Designs, implements, and maintains advanced algorithms for mesh generation and discrete geometry processing using AI technologies. Develops high-performance, memory-efficient software solutions for large geometry data sets. Collaborates with teams to understand customer requirements and translate them into development objectives.

IT Auditor will plan and execute IT and Information Security audits, perform risk assessments, and evaluate IT General Controls. Experience with SOX IT General Controls, IT Application Controls, and systems like SAP and Salesforce is required.

Senior Manager of Layout Design will lead analog and mixed-signal IP projects from specifications to silicon. This role involves customer interaction, problem solving, and collaboration with a global team to develop IPs such as GPIOs, I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, and JTAG.

Senior Staff Engineer will manage the full program engineering lifecycle across multiple projects, ensuring successful delivery of key milestones and customer commitments. Responsibilities include monitoring budgets, schedules, risks, and issues, implementing project management standards, and leading cross-functional teams. Requires a Bachelor's or Master's degree in a relevant field and 5+ years of project/program management experience in engineering, ideally in semiconductor, IP, or ASIC design.

Lead customer deployments of VCS simulation technology, diagnose technical issues, and collaborate with global teams to develop product roadmaps. Drive competitive engagements and provide technical expertise in HDL/HVL methodologies.

Develops emulation solutions for PCIe, CXL, and UCIe protocols using C/C++, Verilog, and scripting languages. Verifies solutions, interacts with customers during deployment, and collaborates with teams to integrate solutions.

Provides expert technical guidance and support for Synopsys Implementation products throughout the RTL-to-GDS flow. Diagnoses and resolves synthesis and place-and-route challenges leveraging deep knowledge of customer designs and Synopsys tools.

Technical Account Specialist will manage relationships with assigned accounts, aligning Synopsys simulation solutions with client business initiatives. Responsibilities include collaborating with global teams, mapping customer requirements to solutions, and driving technical activities to achieve sales goals. Requires a bachelor's degree in a relevant field, experience with Synopsys simulation tools, and strong communication and problem-solving skills. Travel up to 50% is required.

Experienced ASIC Digital Design Engineer with 5-10 years of IP and SoC verification experience sought. Expertise in Synopsys tools (VCS, Verdi, VMS, HVP, VIPs) and methodologies required. Strong leadership, communication, and mentoring skills essential. Bachelor's degree in electronics, electrical, or computer engineering.

Senior R&D Engineer develops and maintains software modules, collaborates with a team, and researches solutions to identified problems. Requires a BS in Electrical Engineering and 5 years' experience in EDA solutions, semiconductor design, or foundries.

Validation & Verification Engineer with 5+ years of experience in hardware and software co-verification. Expertise in Linux environments, scripting languages (bash, tcsh), and hardware installation/maintenance. Requires strong analytical skills, travel flexibility, and collaboration abilities.

Staff Engagement Applications Engineer with 4+ years of experience in synthesis or place and route (P&R) for CPU/GPU/NPU designs. Demonstrates differentiated PPA results and provides technical support to key customers. Utilizes scripting languages and stays updated on ASIC design flow advancements.

Designs DDR I/O circuits for high-performance silicon IP, ensuring compliance with industry standards and customer requirements. Develops and optimizes analog/mixed-signal circuit architectures. Executes circuit design tasks using advanced CMOS processes and state-of-the-art layout methodologies. Collaborates with internal development teams to integrate analog blocks into ASIC and SoC designs.

Staff ASIC RTL Design Engineer with 4+ years of experience in designing complex, high-performance IP cores. Expertise in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Proficient in synthesizable Verilog/SystemVerilog, simulation tools, and design flows.

Functional Safety Application Engineer will act as a technical advisor for deep engagements on functional safety and Ansys medini analyze. Deliver compelling product presentations, demonstrations, and technical discussions. Consult and advise clients on system implementation, ensuring adherence to technical standards and safety requirements. Provide expert guidance and address customer queries on tool usage, functional safety lifecycle, and technical implementations. Partner with channel application engineers to accelerate their onboarding, proficiency, and successful adoption of Ansys medini analyze. Collaborate across sales, R&D, marketing, channel partners, and customers on functional safety initiatives and technical proof-of-concept projects. Conduct hands-on workshops, webinars, and trainings to educate customers and partners on tool usage and best practices. Acquire knowledge and support related areas such as SOTIF and cybersecurity, expanding the breadth of customer solutions.