6574 santa cruz de tenerife English-speaking jobs in Madrid

Staff Engagement Applications Engineer with 4+ years of experience in synthesis or place and route (P&R) for CPU/GPU/NPU designs. Demonstrates differentiated PPA results and provides technical support to key customers. Utilizes scripting languages and stays updated on ASIC design flow advancements.

Senior Staff Engineer will serve as the single point of contact for post-silicon debug activities, enabling Product Requirement Documents (PRDs) and working to enable IP as a product development platform. Requires hands-on experience in post-silicon test setups, sound knowledge of Digital/AMS chip design and post-silicon debug, and a BS or MS degree in Electrical Engineering with 6+ years of experience.

Functional Safety Application Engineer will act as a technical advisor for deep engagements on functional safety and Ansys medini analyze. Deliver compelling product presentations, demonstrations, and technical discussions. Consult and advise clients on system implementation, ensuring adherence to technical standards and safety requirements. Provide expert guidance and address customer queries on tool usage, functional safety lifecycle, and technical implementations. Partner with channel application engineers to accelerate their onboarding, proficiency, and successful adoption of Ansys medini analyze. Collaborate across sales, R&D, marketing, channel partners, and customers on functional safety initiatives and technical proof-of-concept projects. Conduct hands-on workshops, webinars, and trainings to educate customers and partners on tool usage and best practices. Acquire knowledge and support related areas such as SOTIF and cybersecurity, expanding the breadth of customer solutions.

Deliver comprehensive DFT solutions to customers designing digital ICs. Provide technical expertise during design planning, implementation, and silicon bring-up. Implement and validate DFT solutions for Scan/MBIST/1687, including architecture planning, pattern generation, and diagnostics analysis.

Staff ASIC RTL Design Engineer with 4+ years of experience in designing complex, high-performance IP cores. Expertise in data path and control path design, including Reed Solomon FEC, BCH codes, and MAC SEC engines. Proficient in synthesizable Verilog/SystemVerilog, simulation tools, and design flows.

Drive revenue growth and achieve sales targets by developing and executing strategic account plans for enterprise clients in the semiconductor industry. Build and maintain relationships with key decision-makers, identify new business opportunities, and collaborate with technical teams to deliver tailored solutions.

Senior DevOps Engineer (AI) will lead DevOps, deployment, and integration of AI-powered products. Responsibilities include acting as the interface between research and deployment, managing releases, and designing and evolving the build environment. Requires 5+ years experience in DevOps, SRE, or similar role with expertise in cloud deployments, CI/CD, and Docker/Kubernetes.

Provides advanced technical debugging support for Totem-SC and Totem, collaborating with R&D teams to resolve complex issues. Supports certification and evaluation flows for analog IP and power integrity tools, delivering on-site or remote technical support to Korean customers.

Experienced R&D Engineer sought for advanced packaging, auto routing, and physical design automation. Strong programming and EDA software development skills required. Expertise in physical design routing solutions and ability to work independently are essential. Excellent communication skills for influencing stakeholders.

Validation & Verification Engineer with 5+ years of experience in hardware and software co-verification. Expertise in Linux environments, scripting languages (bash, tcsh), and hardware installation/maintenance. Requires strong analytical skills, travel flexibility, and collaboration abilities.

Provide expert-level support for Synopsys PrimeTime, leading technical evaluations and delivering customer training. Collaborate with R&D, marketing, and sales to relay customer feedback and drive product enhancements. Support customers through advanced timing analysis challenges and develop technical documentation.

Develops emulation solutions for PCIe, CXL, and UCIe protocols using C/C++, Verilog, and scripting languages. Verifies solutions, interacts with customers during deployment, and collaborates with teams to integrate solutions.

Designs, implements, and maintains advanced algorithms for mesh generation and discrete geometry processing using AI technologies. Develops high-performance, memory-efficient software solutions for large geometry data sets. Collaborates with teams to understand customer requirements and translate them into development objectives.

Senior Applications Engineer providing technical support and expertise for Synopsys products to key foundry customers. Responsibilities include managing runsets, troubleshooting issues, and collaborating with sales teams. Requires a solid understanding of ASIC design flow, VLSI, and CAD engineering principles.

Experienced engineer with 5-8 years in Physical Verification (PV) for advanced process nodes. Develops and validates DRC, LVS, and Fill runsets for Synopsys IC Validator. Proficient in EDA tools (IC Validator, Calibre, Pegasus) and scripting languages (Perl, Tcl, Python). Collaborates with foundries and customers to ensure successful PV solution deployment.

Senior RTL Design Lead with 8+ years of experience leading complex ASIC digital subsystems from concept to silicon. Expertise in RTL coding, low power design, DFT architectures, and industry-standard protocols. Proven ability to lead cross-functional teams and mentor junior engineers.

Leads digital design and verification activities for advanced SERDES products. Analyzes and interprets specifications, drives test plan creation and execution, and oversees design flows for CDC, synthesis, DFT, and low-power methodologies. Collaborates with verification teams, cross-functional teams, and mentors junior engineers. Requires an MSEE (preferred) or equivalent with 5+ years' experience in digital design and verification, proficiency in Verilog or VHDL, and knowledge of high-speed digital and mixed-signal design.

Mixed-Signal Verification Engineer will execute CoSim verification tasks, build and run simulations, debug mixed-signal failures, and collaborate with analog and digital designers. Requires a Master's degree in Electronics Engineering or related field, understanding of digital verification fundamentals, proficiency in System Verilog, and strong debugging skills.

This role supports advanced photolithography process Mask Synthesis tools, including script development and recipe creation. Provides technical support and consultation to customers, delivers training, and collaborates on joint projects. Requires strong scripting skills, experience in OPC, lithography rule checks, and patterning applications, and the ability to communicate effectively with global customers.

Product Engineering Manager to support and drive product success in the VLSI domain. Collaborate with cross-functional teams to define, develop, and execute product engineering strategies. Minimum 8 years of experience in VLSI product engineering with strong exposure to analog and digital SoC design flows and methodologies.